The article introduces a dual-port FeFET design to address pass disturb in vertical NAND storage. It explains the challenges faced by single-port FeFETs and demonstrates the effectiveness of the proposed dual-port design. The content covers the origin of pass disturb, experimental verifications, and integration into highly scaled vertical NAND arrays. Detailed insights are provided on the structural modifications, operational principles, and experimental validations of the dual-port FeFET design.
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arxiv.org
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