Omni 3D: A BEOL-Compatible 3D Logic Architecture with Integrated Power, Signal, and Clock Routing

Konsep Inti

Omni 3D is a 3D-stacked device architecture that efficiently integrates power, signal, and clock routing with BEOL-compatible transistors, enabling improved energy efficiency and area utilization compared to state-of-the-art complementary FET (CFET) designs.

Abstrak

The paper presents Omni 3D, a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves metal layers for both signal/power with FETs in 3D, providing fine-grained, all-sided access to the FET active regions and maximizing 3D standard cell design flexibility. This is in contrast to approaches such as back-side power delivery networks (BSPDNs), complementary FETs (CFETs), and stacked FETs.

The key innovations of Omni 3D include:

1. One of the power rails is lifted above the upper FET to eliminate tall vias that limit the channel width in CFETs, enabling 3-track cell heights that maintain comparable drive strength of 4-track CFETs.
2. Signal pins are defined on both the top and bottom sides as input (I) and output (Z) for double-side routing.
3. An interleaved metal (IM) layer is introduced between nFET and pFET to provide extra intra-cell routing tracks.

The authors explore multiple Omni 3D variants, including with and without the IM layer, and optimize these variants using a virtual-source BEOL-FET compact model. They establish a physical design flow that efficiently utilizes the double-side routing in Omni 3D and perform a thorough design-technology-co-optimization (DTCO) of the Omni 3D device architecture.

From their design flow, the authors project a 2.0× improvement in the energy-delay product and a 1.5× reduction in area compared to the state-of-the-art CFETs with BSPDNs.

Statistik

Omni 3D achieves a 2.0× improvement in energy-delay product and a 1.5× reduction in area compared to state-of-the-art CFETs with back-side power delivery networks.
Omni 3D reduces wire delay by 35.0% and driver delay by 36.0% compared to CFETs.
Omni 3D reduces net switching energy by 24.6% compared to CFETs.

Kutipan

"Omni 3D arbitrarily interleaves metal layers for both signal/power with FETs in 3D (i.e., nFETs and pFETs are stacked in 3D)."
"Importantly, the routing flexibility of Omni 3D is enabled by double-side routing and an interleaved metal (IM) layer for inter- and intra-cell routing, respectively."
"From our design flow, we project 2.0× improvement in the energy-delay product and 1.5× reduction in area compared to the state-of-the-art CFETs with BSPDNs."

Wawasan Utama Disaring Dari

Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock

by Suhyeong Cho... pada arxiv.org 09-26-2024

https://arxiv.org/pdf/2409.16608.pdf

Pertanyaan yang Lebih Dalam

How can the power grid design in Omni 3D be further optimized to minimize inductive loops and ensure robust power delivery?

To further optimize the power grid design in Omni 3D and minimize inductive loops, several strategies can be employed:

Enhanced Power Distribution Network (PDN) Design: The current split PDN in Omni 3D, with Vdd on the bottom side and Vss on the top side, can be refined by implementing a more balanced distribution of power rails. This involves mirroring the PDN on both sides to ensure that the return paths for current are as short as possible, thereby reducing inductive loops.

Layer Optimization: The use of additional intermediate metal layers can help in distributing power more evenly across the chip. By strategically placing power and ground layers, the inductance can be minimized. For instance, ensuring that power and ground layers are adjacent can help in reducing the loop area, which is critical for minimizing inductive effects.

Inductance-aware Routing: Implementing inductance-aware routing algorithms during the physical design phase can help in identifying and mitigating potential inductive loops. This includes analyzing the layout for critical paths and ensuring that high-frequency signals do not share routing with power lines, which can exacerbate inductive coupling.

Decoupling Capacitors: The strategic placement of decoupling capacitors throughout the power grid can help in stabilizing the voltage levels and reducing the effects of inductive loops. These capacitors can act as local energy reservoirs, providing immediate power to the active circuits and smoothing out voltage fluctuations.

Simulation and Modeling: Utilizing advanced simulation tools to model the power grid's behavior under various load conditions can help identify potential issues before fabrication. This includes using electromagnetic simulation tools to analyze the inductive effects and optimize the layout accordingly.

By implementing these strategies, the Omni 3D architecture can achieve a more robust power delivery system that minimizes inductive loops, ensuring efficient operation at high frequencies and under varying load conditions.

What are the potential challenges and trade-offs in scaling Omni 3D to even smaller technology nodes beyond the sub-2nm node considered in this work?

Scaling Omni 3D to technology nodes smaller than sub-2nm presents several challenges and trade-offs:

Device Variability: As technology nodes shrink, the variability in device performance increases due to factors such as random dopant fluctuations and line-edge roughness. This can lead to significant challenges in maintaining consistent performance across the chip, necessitating more sophisticated design techniques to mitigate these effects.

Thermal Management: With increased transistor density, managing heat dissipation becomes critical. At smaller nodes, the power density increases, which can lead to thermal hotspots. Effective thermal management strategies, such as advanced cooling techniques or thermal-aware design practices, will be essential to ensure reliable operation.

Interconnect Scaling: The scaling of interconnects poses a significant challenge as resistance and capacitance increase with smaller dimensions. This can lead to increased delay and power consumption. Innovations in interconnect materials and structures, such as using lower resistivity materials or advanced routing techniques, will be necessary to address these issues.

Complexity of Design and Manufacturing: As the design rules become more complex, the physical design and manufacturing processes must evolve. This includes the need for more advanced lithography techniques and tighter control over fabrication processes to ensure yield and performance.

Integration of Diverse Technologies: As Omni 3D aims to integrate various device technologies (logic, memory, RF), ensuring compatibility and performance across these different technologies becomes increasingly complex. This requires careful design and optimization to balance the performance characteristics of each technology.

Cost Implications: The cost of developing and manufacturing at smaller nodes can be significantly higher due to the need for advanced materials, equipment, and processes. This can impact the economic viability of scaling down, especially for applications that do not require the highest performance.

In summary, while scaling Omni 3D to smaller technology nodes offers potential performance benefits, it also introduces significant challenges that must be carefully managed through innovative design and engineering solutions.

How can the Omni 3D architecture be extended to enable heterogeneous integration of different device technologies (e.g., BEOL-compatible logic, memory, and analog/RF) in a 3D stack?

Extending the Omni 3D architecture to enable heterogeneous integration of different device technologies can be achieved through several strategies:

Layered Device Integration: By utilizing the 3D stacking capabilities of Omni 3D, different device technologies can be integrated in separate layers. For instance, BEOL-compatible logic can be placed in one layer, while memory technologies (such as RRAM or SRAM) can occupy another. This allows for optimized performance characteristics for each technology while maintaining close proximity for high-speed interconnects.

Interconnect Optimization: The architecture can be designed to include specialized interconnects that cater to the specific needs of different technologies. For example, high-speed interconnects can be used for logic and memory communication, while lower-speed, lower-power interconnects can be employed for analog/RF components. This tailored approach ensures that each technology operates efficiently within the 3D stack.

Thermal Management Solutions: Heterogeneous integration often leads to varying thermal profiles across different technologies. Implementing advanced thermal management solutions, such as micro-channel cooling or thermal vias, can help dissipate heat effectively, ensuring that all components operate within their optimal temperature ranges.

Design for Testability (DFT): As different technologies are integrated, ensuring testability becomes crucial. The Omni 3D architecture can incorporate DFT techniques that allow for efficient testing of each technology layer, facilitating easier identification of faults and improving overall reliability.

Standardized Interfaces: Developing standardized interfaces for communication between different technologies can simplify integration. This includes defining protocols and electrical characteristics that allow for seamless interaction between logic, memory, and analog/RF components.

Advanced EDA Tools: The development of specialized Electronic Design Automation (EDA) tools that support heterogeneous integration will be essential. These tools should be capable of handling the complexities of 3D design, including thermal, electrical, and mechanical considerations, to optimize the performance of the integrated stack.

By implementing these strategies, the Omni 3D architecture can effectively support the heterogeneous integration of various device technologies, enhancing performance and enabling new applications in advanced computing systems.