The paper presents a CMOS-based analog spiking neuron circuit that uses two voltage-controlled oscillators (VCOs) with opposite sensitivities to the internal control voltage. This allows the neuron to transmit and receive analog information through the frequency and width of pulses, making the system robust to noise like digital implementations.
The proposed neuron circuit is used to construct a spiking neural network (SNN) reservoir with a simple regular network topology, where each neuron is connected to only 4 neighboring neurons. This hardware-friendly network structure is combined with a counter-based readout circuit to simplify the implementation.
The authors develop behavioral models of the neuron and weighting circuits to enable efficient system-level simulations. They demonstrate the feasibility of the proposed physical reservoir computing system through experiments on short-term memory, exclusive OR, and spoken digit recognition tasks. The results show the scalability of the approach, with performance improving as the number of neurons is increased.
The key advantages of the proposed system are its hardware-friendliness, robustness to noise, and the ability to dynamically capture the state of each neuron. This provides a useful platform to study the relationship between physical dynamics and computational capability for advancing physical reservoir computing towards practical applications.
Na inny język
z treści źródłowej
arxiv.org
Głębsze pytania