核心概念
Heterogeneous architectures with custom accelerators enhance energy efficiency in edge computing.
統計資料
"The fabricated chip can operate from 0.8 V to 1.2 V, achieving a maximum frequency of 170 MHz and 470 MHz, respectively."
"Power consumption ranges from 270 µW at 32 kHz and 0.8 V, to 48 mW at 470 MHz and 1.2 V."
"Energy benefits of 4.9 × and 4.8 × gained by exploiting the integrated CGRA accelerator and IMC accelerator, respectively."
引述
"To overcome these limitations, we introduce in this paper the eXtendible Heterogeneous Energy-Efficient Platform (X-HEEP)."
"The resulting design, called HEEPocrates, has been implemented both in field programmable gate arrays (FPGAs) on multiple Xilinx chips, for prototyping and exploration, and in silicon with TSMC 65 nm low-power CMOS technology."