المفاهيم الأساسية
This paper presents an interconnect obfuscation methodology at the Register-Transfer Level (RTL) using Switch Boxes (SBs) constructed of Polymorphic Transistors to protect integrated circuit designs from unauthorized use and illegal overproduction. Security-aware high-level synthesis algorithms are also introduced to strategically assign RTL interconnects to functional units in a way that corrupts multiple outputs when the polymorphic SBs are incorrectly unlocked.
الملخص
The paper discusses an RTL interconnect obfuscation method using polymorphic transistors to construct Switch Boxes (SBs). Polymorphic transistors can exhibit both n-type and p-type behavior based on the voltage levels applied to their control and polarity gates, enabling logic encryption and camouflaging.
The key highlights are:
- Polymorphic SBs are designed using the same transistor count as their CMOS counterparts, but with more key-bit combinations to confuse attackers.
- Security-aware high-level synthesis algorithms are presented to strategically assign RTL interconnects to functional units that impact multiple outputs. This ensures that when a polymorphic SB is inserted at those locations, incorrect key-bit identification would corrupt all the affected outputs.
- The obfuscated design is tested against the SMT-based RTL Logic Attack, and the results show that the method is resilient, with the attack timing out after 10 hours without deciphering the key.
The paper aims to provide a secure hardware generation approach at the higher RTL abstraction level, which has fewer design components compared to gate-level obfuscation techniques that may require expensive re-synthesis cycles.
الإحصائيات
The paper does not contain any specific numerical data or statistics. It focuses on the methodology and evaluation of the proposed RTL interconnect obfuscation approach.
اقتباسات
The paper does not contain any direct quotes that are particularly striking or support the key logics.