Conceitos Básicos
Proposing an LLM-assisted HDL debugging framework, HDLdebugger, to streamline and automate the process of debugging Hardware Description Languages for chip design.
Estatísticas
"Our proposed method outperforms all 13 state-of-the-art benchmarks."
"VeriGen w/ SFT achieves a Pass-Rate of 67.55%."
"RTLCoder w/ SFT has a Pass-Rate of 64.21%."
Citações
"The proposed framework automates and streamlines the process of debugging Hardware Description Languages for chip design."
"Our experiments demonstrate that our approach surpasses domain-specific solutions in the context of HDL debugging."