The content discusses the implementation of T1 flip-flops (T1-FF) in Rapid Single-Flux Quantum (RSFQ) systems to enhance efficiency. By using T1-FFs, the full adder function can be achieved with reduced area requirements compared to conventional methods. The integration of multiphase clocking helps control fanin signals efficiently, reducing network area by up to 6% and optimizing a 128-bit adder by up to 25%. The article details the operation of T1-FFs, challenges related to input signal timing, and proposes solutions like multiphase clocking for gate-level pipelining overhead. The methodology involves replacing parts of the SFQ network with T1-FFs, assigning clock phases, and inserting DFFs for timing requirements. Experimental results show improvements in area reduction and path-balancing DFFs using T1-aware technology mapping.
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by Rassul Baira... kl. arxiv.org 03-12-2024
https://arxiv.org/pdf/2403.05901.pdfDybere Forespørgsler