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Prefetching-based Scheme to Mitigate Conflict-based Cache Side-channel Attacks


Conceptos Básicos
PCG combines adding victim-irrelevant cache occupancy changes and reducing victim-relevant cache occupancy changes to disrupt attackers by generating noisy and indistinguishable cache access patterns.
Resumen
The paper proposes a novel prefetching-based scheme called PCG to mitigate conflict-based cache side-channel attacks. PCG has two key components: Attack Aware Module (AAM): Identifies abnormal cache sets that may be exploited by attackers based on the number of MSHR misses. Marks the identified abnormal cache sets in the dangerSet register. Observation Confused Module (OCM): Reduces victim-relevant cache footprints by: Assigning the highest replacement priority to cache lines potentially accessed by the victim. Prefetching back the evicted victim cache lines. Adds victim-irrelevant cache footprints as interfering noise by: Triggering random forward or backward prefetches on cache misses. Adjusting the prefetching addresses to balance the access across cache sets. The evaluation results show that PCG provides robust security superior to existing solutions, while without resulting in significant performance degradation. PCG even shows an average performance improvement of about 1.64% on the SPEC CPU 2017 benchmark suite, with only 1.26% overhead on hardware resource consumption.
Estadísticas
The proportion of MSHR misses among all cache accesses exceeds 20% for the Spectre-type attack programs, while it is less than 3.75% for most of the benign programs. The proportions of MSHR misses among all cache misses are much higher for all the attack programs (more than 96%) compared to less than 60% for all benign programs.
Citas
"To defend against conflict-based cache side-channel attacks, cache partitioning or remapping techniques were proposed to prevent set conflicts between different security domains or obfuscate the locations of such conflicts. But such techniques complicate cache design and may result in significant performance penalties." "There have been some studies proposing prefetching-based mechanisms, such as Disruptive Prefetching (DP) and PREFENDER, to defend against cache side-channel attacks. Such mechanisms do not target the design of secure cache architecture. Instead, they are proposed based on the fact that hardware prefetchers speculatively bring data/instructions into the cache, including those that have never actually been used by the victim, thereby which can be utilized as noise to confuse the attacker's observation of the victim's cache access pattern."

Consultas más profundas

How can PCG be extended to protect against other types of microarchitectural side-channel attacks beyond conflict-based cache attacks

PCG can be extended to protect against other types of microarchitectural side-channel attacks by incorporating additional defense mechanisms tailored to specific attack vectors. For example, to defend against timing-based side-channel attacks, PCG could implement techniques to introduce random delays or jitter in cache access patterns. This would make it challenging for attackers to extract sensitive information based on timing variations. Additionally, for power consumption side-channel attacks, PCG could integrate strategies to manipulate power usage patterns through prefetching or cache management, thereby masking any power-related signals that could be exploited by attackers. By customizing its prefetching and cache manipulation strategies to counter different types of side-channel attacks, PCG can provide comprehensive protection across various microarchitectural vulnerabilities.

How effective would PCG be against attackers that can reverse-engineer the prefetching policies used by PCG

Against attackers capable of reverse-engineering the prefetching policies used by PCG, the effectiveness of PCG may be compromised to some extent. If attackers can accurately predict the prefetching behavior and adjust their attack strategies accordingly, they may find ways to bypass the defense mechanisms implemented by PCG. However, PCG still offers a significant advantage in terms of introducing noise and confusion into the cache access patterns, making it more challenging for attackers to extract meaningful information even if they understand the prefetching policies. By continuously evolving and enhancing the complexity of prefetching algorithms and cache manipulation techniques, PCG can maintain a strong defense against sophisticated attackers attempting to reverse-engineer its policies.

What are the potential trade-offs between the degree of prefetching used by PCG and the resulting performance and security characteristics

The degree of prefetching used by PCG can have a significant impact on both performance and security characteristics. A higher prefetching degree can introduce more noise and confusion into the cache access patterns, making it harder for attackers to distinguish between victim-related and irrelevant cache footprints. This can enhance security by increasing the complexity of the cache behavior and making it more challenging for attackers to extract sensitive information. However, a higher prefetching degree may also lead to more cache pollution and potential performance degradation, as prefetching unnecessary data can occupy cache resources and impact the efficiency of memory access. On the other hand, a lower prefetching degree may reduce the risk of cache pollution and performance overhead but could potentially weaken the security provided by PCG. Attackers may find it easier to differentiate between victim-related and irrelevant cache footprints with a lower prefetching degree, potentially compromising the defense mechanism. Therefore, finding the right balance between prefetching degree, performance impact, and security effectiveness is crucial in optimizing the overall performance of PCG in mitigating microarchitectural side-channel attacks.
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