This work describes the design and fabrication of embedded FPGAs (eFPGAs) using the 130nm and 28nm CMOS technology nodes, leveraging the open-source "FABulous" framework. The eFPGA technology offers a unique combination of flexibility, low power, and small footprint, making it an ideal tool for data acquisition challenges in collider physics.
The 130nm eFPGA design was successfully tested, demonstrating the basic functionality of the eFPGA through a simple counter test and power measurements. To address the need for increased logic density, enhanced radiation hardness, and reduced power consumption, the design was later transitioned to the 28nm CMOS technology node.
The 28nm eFPGA design was also successfully tested, including a simple counter test, power measurements, and an AXI stream loopback test in the eFPGA. As a proof-of-concept, the 28nm eFPGA was used to implement a Boosted Decision Tree (BDT) model for machine learning-based pileup classification in a simulated particle detector readout scenario. The BDT model was successfully synthesized and configured onto the eFPGA, achieving 100% accuracy compared to the golden software results.
Further development of the eFPGA technology and its application to collider detector readout is discussed, including the need for larger logical capacity, improved radiation tolerance, and co-design of high-performance sensor processing algorithms.
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arxiv.org
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