Finite Control Set Model Predictive Control with Switching Frequency Limiting via Slack Variables

Core Concepts

The core message of this article is to formulate a finite control set model predictive control (FCS-MPC) method that limits the switching frequency by penalizing the slack variable corresponding to a constraint on the switching frequency.

Abstract

The article proposes an extension to finite control set model predictive control (FCS-MPC) to limit the switching frequency. The authors introduce a switching frequency constraint with a slack variable and penalize the slack variable in the cost function. This is in contrast to the previous work on FCS-MPC with switching frequency tracking, where the switching frequency was tracked directly. The key highlights and insights are: The switching frequency is captured with an infinite impulse response (IIR) filter and bounded by an inequality constraint. The corresponding slack variable is penalized in the cost function. To solve the problem efficiently, a sphere decoder with a computational speed-up is presented. The speed-up is achieved by exploiting a provable lower bound that incorporates the prediction model of the slack variable. The proposed switching frequency limiting FCS-MPC (FL-MPC) is benchmarked against the switching frequency tracking FCS-MPC (FT-MPC) in various scenarios. FL-MPC is shown to perform better than FT-MPC in terms of current tracking performance, while maintaining a similar average switching frequency. The computational speed-up for the sphere decoder in FL-MPC is demonstrated, with significant reductions in the maximum solving time and improvements in the 70th and 95th percentiles compared to FT-MPC.

Stats

The current total demand distortion (TDD) is improved by 5.1% for the FL-MPC over the FT-MPC at a lower average switching frequency. The current tracking error is improved by 9.8% for the power ramp-up and by 56% for the switching frequency step-up when using FL-MPC compared to FT-MPC.

Quotes

"To avoid the tuning process altogether, alternative MPC formulations have been proposed to set the switching frequency directly by fixing the number of possible switching transitions in a given time interval, see [18]–[22] and the references therein." "One of the first attempts to include constraints (in particular, current constraints) in the sphere decoder has been made in [24], [25]. The authors have proposed an algorithm to map the state constraints to the input constraints, if the state itself has a linear prediction model."

Key Insights Distilled From

Switching Frequency Limitation with Finite Control Set Model Predictive Control via Slack Variables

by Luca M. Hart... at arxiv.org 04-19-2024

https://arxiv.org/pdf/2312.05916.pdf

Deeper Inquiries

How can the proposed switching frequency limiting approach be extended to other power converter topologies beyond the 3-level neutral-point-clamped converter considered in this work

The proposed switching frequency limiting approach can be extended to other power converter topologies by adapting the constraints and penalty terms in the optimization problem to suit the specific characteristics of the new converter. For example, in a different converter topology like a multilevel inverter or a dual-active-bridge converter, the constraints on the switching frequency can be modified to account for the unique switching patterns and voltage levels of these converters. Additionally, the penalty weights for the slack variables related to the switching frequency constraints can be adjusted based on the switching characteristics of the new converter. By customizing the constraints and penalties, the FL-MPC can be tailored to effectively limit the switching frequency in various power converter topologies.

What are the potential trade-offs between current tracking performance and switching frequency limiting in different application scenarios, and how can the controller be further tuned to balance these objectives

The potential trade-offs between current tracking performance and switching frequency limiting depend on the specific requirements of the application scenario. In scenarios where minimizing switching losses or reducing electromagnetic interference is critical, prioritizing switching frequency limiting over current tracking may be more beneficial. On the other hand, in applications where precise current control is paramount, sacrificing some degree of switching frequency limitation to enhance current tracking performance may be necessary. To balance these objectives, the controller can be further tuned by adjusting the weighting factors λsw and λu in the cost function. By fine-tuning these parameters, the trade-off between current tracking and switching frequency limiting can be optimized based on the specific requirements of the system. Additionally, incorporating adaptive control strategies that dynamically adjust the weighting factors based on real-time system conditions can help achieve a more flexible and responsive balance between current tracking and switching frequency limiting.

Given the computational improvements demonstrated, how could the proposed FL-MPC be implemented on embedded hardware, such as field-programmable gate arrays (FPGAs), to enable real-time control of high-speed power electronics systems

The computational improvements demonstrated in the proposed FL-MPC make it well-suited for implementation on embedded hardware, such as field-programmable gate arrays (FPGAs), to enable real-time control of high-speed power electronics systems. To implement FL-MPC on FPGAs, the algorithm can be optimized for hardware acceleration by leveraging the parallel processing capabilities of FPGAs. One approach to implementing FL-MPC on FPGAs is to design custom hardware accelerators for the critical computational tasks, such as the sphere decoding algorithm and the optimization problem solver. By offloading these computationally intensive tasks to dedicated hardware modules within the FPGA, real-time performance can be achieved. Furthermore, the use of fixed-point arithmetic and optimized hardware architectures can further enhance the computational efficiency of FL-MPC on FPGAs. By carefully designing the hardware implementation to exploit the parallelism and reconfigurability of FPGAs, FL-MPC can be efficiently deployed for high-speed control of power electronics systems in embedded applications.