The paper introduces Siracusa, a 16 nm heterogeneous system-on-chip (SoC) designed for extended reality (XR) applications. Siracusa features a cluster of 8 RISC-V cores and a specialized neural network accelerator called N-EUREKA, which is tightly coupled to a 4 MB on-chip MRAM memory for storing neural network weights.
The key highlights of the Siracusa SoC are:
Heterogeneous Architecture: Siracusa combines a RISC-V core cluster for general-purpose computing and signal processing with the N-EUREKA neural network accelerator. The two compute engines share a low-latency 256 KB L1 memory for efficient collaboration.
At-MRAM Integration: N-EUREKA is tightly coupled to a 4 MB on-chip MRAM memory subsystem, enabling high-bandwidth, low-latency access to neural network weights. This "At-MRAM" integration achieves 1.7x higher throughput and 3x better energy efficiency compared to using MRAM as background memory.
Scalable Weight Memory: Siracusa also includes a 4 MB SRAM tile memory that can be used as additional weight storage for larger neural networks, allowing the system to scale to more complex workloads.
Efficient Collaboration: The RISC-V cores and N-EUREKA accelerator efficiently collaborate through the shared L1 memory, with a configurable priority arbiter managing their access to maximize performance and energy efficiency.
The fabricated Siracusa SoC prototype achieves a peak energy efficiency of 8.84 TOp/J for DNN inference, with an area efficiency of 65.2 GOp/s/mm^2. It demonstrates the benefits of tightly integrating non-volatile memory with a specialized neural network accelerator for energy-efficient edge computing in XR applications.
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