Core Concepts
This work presents a fully-automated verifier for linear time-invariant systems that can decide whether the system satisfies a given signal temporal logic (STL) specification for all initial states and uncertain inputs.
Abstract
The paper presents a fully-automated verifier for linear time-invariant (LTI) systems against signal temporal logic (STL) specifications. The key aspects are:
The verifier combines reachability analysis with a novel model checking approach that tracks dependencies between reachable states and initial states/inputs. This avoids the conservatism of previous reachset temporal logic (RTL) approaches.
The reachability analysis algorithm is designed to be dependency-preserving, allowing the construction of an approximate solution to the differential equation with a guaranteed error bound.
The model checking procedure explicitly keeps track of which initial states and inputs lead to a violation of the STL specification, enabling the identification of safe and unsafe sets.
The overall verifier automatically refines the time step size and truncation order until the specification can be either verified or falsified, guaranteeing termination for decidable problem instances.
The verifier can also be used to identify safe sets of initial states and inputs or to cut away all unsafe states, which is useful for controller synthesis and set-based prediction.
The authors demonstrate the performance of the automated verifier on several challenging benchmark systems.