Core Concepts
Time-domain computing offers energy-efficient solutions for VMM with trade-offs in accuracy and efficiency.
Abstract
The content discusses the merits of time-domain computing for Vector-Matrix-Multiplication (VMM) in comparison to analog and digital approaches. It explores the energy efficiency, accuracy, and scalability of time-domain computing for VMM applications. The analysis includes a detailed investigation of TD-MAC cells, TDC architectures, error tolerance, throughput, and area requirements for different array dimensions and input word widths. The comparison highlights the strengths and weaknesses of each computing domain in terms of energy consumption, throughput, and area efficiency.
Structure:
- Introduction
- Vector-Matrix-Multiplication (VMM) Accelerators
- Analog Computing Schemes
- Time-Domain (TD) Computing
- TD-MAC Cell
- Time-to-Digital Converter (TDC)
- Error Tolerance and Accuracy
- Throughput Comparison
- Area Efficiency
- Conclusion
Stats
"An 89 TOPS/W and 16.3 TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications."
"A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight, and Output and Achieving 351 TOPS/W and 372.4 GOPS."
"A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices."
Quotes
"Analog Versus Digital: Extrapolating from Electronics to Neurobiology."
"A 55-nm, 1.0–0.4V, 1.25-pJ/MAC Time-Domain Mixed-Signal Neuromorphic Accelerator With Stochastic Synapses for Reinforcement Learning in Autonomous Mobile Robots."