Efficient Rust-Based Inference Engine for Deploying Neural Networks on Tiny Embedded Devices
MicroFlow is an open-source, Rust-based TinyML framework that enables efficient deployment of neural networks on highly resource-constrained embedded devices, including 8-bit microcontrollers with only 2kB of RAM.
Optimizing End-to-End Latency for Multi-Component Embedded Systems using High-Level Synthesis Design Space Exploration
This paper presents a novel system-level High-Level Synthesis (HLS) Design Space Exploration (DSE) approach, called EtoE-DSE, that accommodates end-to-end (EtoE) latency and variable timing constraints for complex multi-component application-specific embedded systems.
인텔 Myriad X 임베디드 SoC에서 위성 자세 추정을 위한 AI 및 컴퓨터 비전 가속화
인텔 Myriad X 임베디드 SoC에서 AI와 고전적인 컴퓨터 비전 기술을 결합하여 위성 자세 추정 및 추적 문제를 해결하는 단일 칩 솔루션을 제안한다.
마이크로컨트롤러에서 시계열 분류를 위한 데이터 수집률 감소가 TinyML에 미치는 영향
데이터 수집률 감소가 마이크로컨트롤러에서 TinyML 모델의 성능에 미치는 영향을 분석하여, 자원 제한적 환경에서 효율적인 TinyML 모델 구현을 위한 방안을 제시한다.
Developing Energy-Efficient Deep Learning Accelerators for Embedded Devices using the ElasticAI-Workflow
The ElasticAI-Workflow, consisting of the ElasticAI-Creator toolchain and the Elastic Node hardware platform, enables deep learning developers without FPGA expertise to create and deploy energy-efficient deep learning accelerators on embedded devices.
PEFSL: 임베디드 시스템에서의 적은 샘플 학습을 위한 배포 파이프라인
적은 수의 레이블 데이터로도 효과적인 객체 분류를 수행할 수 있는 FPGA SoC 기반의 적은 샘플 학습 플랫폼을 제안한다.
FPGA SoC上の組み込み型Few-Shot Learningのための展開パイプラインPEFSL
FPGA SoCに組み込み型Few-Shot Learningシステムを実装するための、オープンソースのエンドツーエンドパイプラインPEFSLを提案する。
Efficient Deployment of Few-Shot Learning on FPGA SoCs for Real-Time Object Classification
This paper presents an end-to-end open-source pipeline for deploying a few-shot learning platform for real-time object classification on FPGA SoCs, enabling rapid adaptation to new tasks with minimal resources.
Automated Compression and Deployment of Neural Networks on AURIX TC3xx Microcontrollers
OpTC, an end-to-end toolchain, automatically compresses, converts, and generates C code for deploying various types of neural networks on AURIX TC3xx microcontrollers, enabling efficient execution on resource-constrained embedded devices.
A High-Level Synthesis Approach for Designing Precisely-Timed and Energy-Efficient Embedded Systems
The proposed Hybrid High-Level Synthesis (H-HLS) methodology integrates state-based high-level synthesis (SB-HLS) and performance-driven high-level synthesis (PD-HLS) to enable the design and optimization of application-specific embedded systems with explicit and precise timing specifications.
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