The authors present a novel non-volatile spin transfer torque (STT) assisted spin-orbit torque (SOT) based ternary content addressable memory (TCAM) with 5 transistors and 2 magnetic tunnel junctions (MTJs) for hardware accelerators.
At the device-level, the write characteristics such as write error rate, time, and current are obtained using micromagnetic simulations. The array-level search and write performance are evaluated based on SPICE circuit simulations with layout extracted parasitics for bitcells, accounting for the impact of interconnect parasitics at the 7nm technology node. A search error rate of 3.9x10-11 is projected for exact search while considering various sources of variation.
The resolution of the approximate search operation is quantified under different scenarios to understand the achievable quality. The application-level performance and accuracy of the proposed design are evaluated and benchmarked against other state-of-the-art CAM designs in the context of a CAM-based recommendation system.
The proposed design eliminates the need for a magnetic field for the write operation, improving magnetic immunity compared to previous SOT-CAM designs. The authors perform a comprehensive study of the design in terms of write, exact search, and approximate search, optimizing the layout, array size, and search voltages to ensure accurate search operations.
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