Główne pojęcia
Efficient cell library characterization using Graph Neural Networks for Design Technology Co-Optimization.
Streszczenie
The content discusses the importance of Design Technology Co-Optimization (DTCO) in semiconductor process development. It introduces a novel approach using Graph Neural Networks (GNNs) for rapid and accurate cell library characterization, enabling fast and cost-effective system-level DTCO iterations. The study validates the GNN-based model's accuracy across various technology parameters and PVT corners, showcasing significant speed-ups compared to traditional SPICE simulations. Additionally, it explores system-level metrics and proposes a drive strength interpolation methodology for enhanced PPA in small-to-medium-scale designs.
Structure:
Introduction to DTCO and its significance.
Role of cell library in DTCO iterations.
Challenges with traditional methods of cell library characterization.
Proposal of GNN-based machine learning model.
Validation results on prediction accuracy and speed-up.
Investigation of system-level metrics like WNS, leakage power, dynamic power.
Introduction of fine-grained drive strength interpolation methodology.
Experimental results on system-level predictions and PPA improvement.
Statystyki
Validation with 512 unseen technology corners and over one million test data points shows accurate predictions with MAPE ≤ 0.95%.
Speed-up of 100X compared with SPICE simulations achieved by the proposed GNN-based model.
Cytaty
"Our model achieves precise predictions, with absolute error ≤3.0 ps for WNS."
"Our proposed model surpasses state-of-the-art works in terms of accuracy and generalization performance."