The paper introduces a novel analytical framework for 3D mixed-size placement in heterogeneous face-to-face (F2F) bonded ICs. It addresses the challenges of integrating standard cells and macros in a 3D solution space. The proposed approach includes a dedicated density model, bistratal wirelength model, and macro rotation optimization using MILP formulation. Full-scale GPU acceleration is leveraged for efficient implementation. Experimental results show significant quality score improvement compared to existing methods.
As technology scaling reaches its limits, 3D integrated circuits (ICs) offer a solution by stacking multiple dies vertically. Heterogeneous 3D ICs can benefit from advanced technology nodes for standard cells without worrying about hard IPs' technology node.
Three main variants of 3D ICs are through-silicon-via (TSV) based, monolithic, and face-to-face (F2F) bonding.
Existing methodologies focus on either standard cell or mixed-size designs with macros. Recent placers for F2F bonded 3D ICs mainly concentrate on standard cell placement.
True-3D placers adopt analytical approaches to handle mixed-size placements effectively but lack accurate models for heterogeneous integration.
The proposed framework optimizes instance partitioning and locations in a 3D solution space while resolving topological and physical differences between macros and standard cells.
A novel preconditioner bridges the gap between macros and standard cells, enhancing convergence and runtime efficiency.
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