AssertLLM: An Automatic Assertion Generation Framework for Hardware Verification Using Multiple Large Language Models

Core Concepts

AssertLLM is a novel framework that leverages the power of multiple large language models (LLMs) to automate the generation of SystemVerilog Assertions (SVAs) from complex hardware design specifications, improving the efficiency and effectiveness of hardware verification.

Abstract

• Bibliographic Information: Yan, Z., Fang, W., Li, M., Li, M., Liu, S., Xie, Z., Zhang, H. (2025). AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. In 30th Asia and South Pacific Design Automation Conference (ASPDAC ’25) (pp. 1–8). Tokyo, Japan: ACM. https://doi.org/10.1145/3658617.3697756
• Research Objective: This paper introduces AssertLLM, a novel framework that addresses the challenges of automatically generating SystemVerilog Assertions (SVAs) from comprehensive hardware design specifications, aiming to improve the efficiency and quality of hardware verification.
• Methodology: AssertLLM employs three specialized LLMs:
  1. Natural Language Analyzer: Extracts structured information from unstructured natural language specifications.
  2. Waveform Analyzer: Analyzes waveform diagrams to generate behavioral descriptions.
  3. SVA Generator: Translates the extracted information into SVAs, enhanced by Retrieval Augmented Generation (RAG) for improved accuracy.
• Key Findings:
  • AssertLLM successfully generates SVAs from both natural language specifications and waveform diagrams.
  • Evaluation on various designs, including "I2C," "ECG," and "Pairing," demonstrates that 88% of generated SVAs are syntactically and functionally correct.
  • The generated SVAs achieve a high cone of influence (COI) coverage of 97%, indicating their effectiveness in verifying a large portion of the design logic.
• Main Conclusions:
  • AssertLLM significantly outperforms existing methods like GPT-4o and GPT-3.5 in generating accurate and comprehensive SVAs.
  • The framework offers a promising solution for automating the assertion generation process, potentially reducing manual effort and improving verification efficiency.
• Significance: This research contributes to the field of hardware verification by presenting a novel and effective approach for automating SVA generation, a critical but time-consuming task in the design process.
• Limitations and Future Research:
  • The quality of generated SVAs depends on the comprehensiveness of the design specifications.
  • Future research could explore incorporating more sophisticated NLP techniques and expanding the knowledge base for the SVA Generator to further enhance the accuracy and coverage of the generated assertions.

Stats

AssertLLM achieves an 88% success rate in generating SVAs that are both syntactically and functionally correct.
The generated SVAs achieve a 97% cone of influence (COI) coverage.
GPT-4o only achieved 11% accuracy in generating SVAs from natural language specifications.
For the "I2C" design, AssertLLM generated 65 properties: 23 for bit-width, 14 for connectivity, and 28 for function.

Quotes

Key Insights Distilled From

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs

by Zhiyuan Yan,... at arxiv.org 11-25-2024

https://arxiv.org/pdf/2411.14436.pdf

Deeper Inquiries

How can AssertLLM be adapted to handle evolving design specifications and maintain the consistency and correctness of the generated SVAs over time?

AssertLLM can be adapted to handle evolving design specifications and maintain SVA consistency and correctness using several strategies:
1. Incremental SVA Generation and Update:

Change Detection: Implement a mechanism to detect and analyze changes between specification versions. This could involve techniques like text differencing algorithms or even leveraging LLMs for semantic comparison of specification sections.
Targeted SVA Modification: Instead of regenerating all SVAs, focus on modifying those impacted by the specification changes. This requires mapping SVAs back to the specific sections or sentences in the specification that they originated from.
SVA Regression Testing: Develop a regression test suite for the generated SVAs. Whenever specifications are updated, rerun these tests to identify any inconsistencies or regressions introduced by the changes.
2. Specification Version Control and SVA Traceability:

Versioned SVA Database: Maintain a database of generated SVAs linked to specific specification versions. This allows for tracking the evolution of assertions alongside design changes.
SVA Traceability Links: Establish clear traceability links between individual SVAs and the corresponding sections, sentences, or even waveform diagrams in the specification. This aids in understanding the rationale behind each assertion and facilitates updates when specifications evolve.
3. LLM Fine-tuning with Updated Specifications:

Continuous Learning: Periodically fine-tune the LLMs used in AssertLLM (Natural Language Analyzer, Waveform Analyzer, SVA Generator) with updated specification versions. This helps the models adapt to evolving language and design patterns.
Reinforcement Learning from Feedback: Incorporate a feedback loop where verification engineers can validate or correct generated SVAs. This feedback can be used to further fine-tune the LLMs and improve their accuracy over time.
4. Leveraging Formal Verification for Consistency Checking:

Formal Equivalence Checking: When significant architectural changes occur, employ formal equivalence checking techniques to verify that the updated RTL design with the modified SVAs still conforms to the intended behavior of the updated specification.
By implementing these strategies, AssertLLM can become an even more powerful tool for hardware verification, capable of adapting to the dynamic nature of design specifications while ensuring the ongoing reliability and effectiveness of the generated SVAs.

Could the reliance on "golden RTL implementations" for evaluating SVA quality be minimized or eliminated to enable assertion generation earlier in the design cycle?

Yes, the reliance on "golden RTL implementations" for evaluating SVA quality can be minimized or eliminated to enable earlier assertion generation using these approaches:
1. Formal Verification of SVAs against High-Level Models:

Executable Specifications: If the design specifications can be expressed in an executable language (e.g., SystemC, BlueSpec), formal verification tools can be used to directly verify the generated SVAs against these high-level models.
Abstract Model Checking: Create abstract models of the design at a higher level of abstraction than RTL. These models capture the essential behavior without the complexity of the final implementation, allowing for earlier SVA verification.
2. Leveraging Assertion Libraries and Design Patterns:

Reusable Assertion IP: Develop or utilize libraries of pre-verified SVAs for common design blocks or protocols. These assertions can be integrated into AssertLLM and reused across projects, reducing the dependence on golden RTL for validation.
Design Pattern Recognition: Train LLMs to recognize common design patterns within specifications and automatically generate corresponding SVAs based on known-good templates associated with those patterns.
3. Enhanced LLM Reasoning and Simulation-Based Validation:

Symbolic Simulation: Employ symbolic simulation techniques to explore a wider range of design states and behaviors with the generated SVAs, even without a complete RTL implementation.
Constraint Solving: Integrate constraint solving capabilities into AssertLLM to formally reason about the relationships and constraints implied by the specifications and generate SVAs that are more likely to be correct by construction.
4. Shift-Left Verification with Early Feedback Loops:

Collaborative Verification: Encourage early collaboration between designers, verification engineers, and even architects to review and refine the generated SVAs in the context of the evolving design.
Agile Methodologies: Integrate assertion generation and validation into agile design methodologies. This allows for iterative refinement of both specifications and SVAs throughout the design process.
By adopting these methods, the hardware verification process can "shift left," enabling SVA generation and validation earlier in the design cycle, even before a complete RTL implementation is available. This proactive approach can lead to earlier detection of design errors, reducing costly rework and ultimately accelerating the overall design cycle.

What are the ethical implications of using LLMs in safety-critical hardware design, and how can we ensure the reliability and trustworthiness of AI-generated assertions in such contexts?

Using LLMs in safety-critical hardware design presents significant ethical implications that demand careful consideration:
1. Bias and Fairness:

Training Data Bias: LLMs are trained on massive datasets, which may contain biases that could lead to unfair or discriminatory outcomes in safety-critical applications.
Mitigation: Carefully curate and audit training data for bias. Employ techniques like adversarial training to make models more robust to biased inputs.
2. Transparency and Explainability:

Black Box Nature: LLMs can be opaque in their decision-making, making it difficult to understand why a particular assertion was generated. This lack of transparency is problematic in safety-critical systems where accountability is crucial.
Mitigation: Develop methods for explaining LLM-generated assertions. Explore techniques like attention mechanisms to provide insights into which parts of the specification influenced the assertion generation.
3. Verification and Validation Challenges:

Exhaustive Testing Limitations: Exhaustively testing AI-generated assertions in safety-critical systems is challenging due to the vast state space of complex designs.
Mitigation: Combine formal verification techniques with rigorous testing strategies. Develop new methodologies specifically for verifying and validating AI-generated artifacts.
4. Over-Reliance and Deskilling:

Erosion of Expertise: Over-reliance on LLMs could lead to a decline in the critical thinking skills of verification engineers.
Mitigation: Use LLMs as assistive tools to augment, not replace, human expertise. Emphasize the importance of human oversight and critical evaluation of AI-generated outputs.
5. Accountability and Liability:

Responsibility for Errors: Determining accountability when AI-generated assertions fail in safety-critical systems raises complex legal and ethical questions.
Mitigation: Establish clear guidelines and standards for the development and deployment of AI-assisted design tools. Explore mechanisms for shared responsibility between developers, users, and regulators.
Ensuring Reliability and Trustworthiness:

Rigorous Validation and Certification: Develop rigorous validation and certification processes specifically for AI-assisted design tools used in safety-critical applications.
Formal Methods Integration: Integrate formal verification techniques into the LLM workflow to provide stronger guarantees about the correctness of generated assertions.
Human-in-the-Loop: Maintain a strong human-in-the-loop approach, where experienced engineers review, validate, and ultimately take responsibility for the final design decisions.
Open Standards and Collaboration: Foster open standards and collaboration within the industry and with regulatory bodies to establish best practices and guidelines for the ethical and responsible use of LLMs in safety-critical hardware design.
Addressing these ethical implications and ensuring the reliability and trustworthiness of AI-generated assertions is paramount for the responsible adoption of LLMs in safety-critical hardware design. A multi-faceted approach that combines technical advancements with ethical considerations and robust governance frameworks is essential to fully realize the benefits of AI while mitigating potential risks in these sensitive domains.