Basilisk는 오픈 소스 EDA 도구를 활용하여 Iguana SoC를 최적화하여 성능과 코어 활용도를 향상시켰다.
オープンソースのEDAツールを使用して、Basiliskと呼ばれるRISC-Vシステムオンチップの性能を大幅に向上させた。合成とレイアウトの最適化により、クロック周波数を2.3倍、コア利用率を55%まで高めた。
Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow, achieves competitive performance by enhancing open-source electronic design automation (EDA) tools and the physical design of the Iguana RISC-V SoC.
DRAM 마이크로아키텍처와 오류 특성에 대한 정확한 이해를 위해 다양한 역공학 기법을 활용하여 DRAM 칩의 내부 구조와 동작을 심층적으로 분석하였다.
The authors conduct a comprehensive study to better understand the DRAM microarchitecture and activate-induced bitflip (AIB) characteristics of modern DRAM chips, leveraging three different reverse-engineering techniques and their recent knowledge of address mapping and data swizzling.
An integrated framework for automated generation and physical design of application-specific superconducting quantum architectures.
A new General Tensor Accelerator (GTA) architecture that combines systolic array and vector processing units to efficiently process tensor operators with arbitrary computational workload and precision.
FPGA에서 효율적인 작은 곱셈기를 구현하기 위해 불완전한 부분 곱셈기를 사용하는 새로운 방법을 제안한다.
本研究では、FPGAにおいて効率的に実装できる新しい種類の不完全論理ベースサブ乗算器を提案し、乗算器タイリング手法と組み合わせることで、従来の手法と比べて資源使用量を削減できることを示す。
This work proposes a novel class of incomplete logic-based multiplier tiles that map efficiently to modern FPGAs, demonstrating improvements over state-of-the-art designs.