Design and Implementation of a Pipelined Full Posit Processing Unit for RISC-V Processors

This work presents the design, implementation, and integration of a full posit processing unit (FPPU) capable of directly implementing in hardware the four arithmetic operations (add, sub, mul, div and fma), the inversion, and the float-to-posit and posit-to-float conversions. The FPPU is integrated into the low-power Ibex RISC-V core, extending the RISC-V ISA to support posit arithmetic.