Securing Hardware Designs Against Unauthorized Use and Overproduction Through Polymorphic Switch Boxes and Security-Aware High-Level Synthesis
This paper presents an interconnect obfuscation methodology at the Register-Transfer Level (RTL) using Switch Boxes (SBs) constructed of Polymorphic Transistors to protect integrated circuit designs from unauthorized use and illegal overproduction. Security-aware high-level synthesis algorithms are also introduced to strategically assign RTL interconnects to functional units in a way that corrupts multiple outputs when the polymorphic SBs are incorrectly unlocked.
ChatFuzz: An ML-Powered Hardware Fuzzer for Efficient Vulnerability Detection in Complex Processors
ChatFuzz leverages large language models and reinforcement learning to generate complex, interdependent, and pseudo-random instruction sequences that significantly improve hardware coverage and vulnerability detection in modern processors.
Exploiting AMD SEV-SNP's VMM Communication Exception (#VC) to Break Confidentiality and Integrity Guarantees
The WESEE attack abuses the VMM Communication Exception (#VC) in AMD SEV-SNP to compromise the confidentiality and integrity of guest VMs by injecting malicious #VCs that induce arbitrary register and memory read/write operations.
Trojan Playground: Reinforcement Learning Framework for Hardware Trojan Insertion and Detection
Automated RL framework for HT insertion and detection to address benchmark limitations and human bias.
The Emergence of Hardware Fuzzing: A Critical Review
Hardware fuzzing is crucial for identifying vulnerabilities in complex hardware designs.
DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks
DECOR is a randomized algorithm-based method that significantly decreases the correlation between locked circuit netlist and correct key values, enhancing resilience against ML-based attacks.
WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors
WhisperFuzz introduces a novel white-box fuzzer with static analysis to detect and locate timing vulnerabilities in processors, addressing deficiencies in existing fuzzers.
A Scalable Formal Verification Methodology for Data-Oblivious Hardware by Lucas Deutschmann et al.
The authors propose a novel methodology to verify data-oblivious behavior in hardware using standard property checking techniques, ensuring scalability even to complex out-of-order cores.
Enhancing Logic Locking Against Machine Learning-Based Attacks
The author presents DECOR, a method to enhance logic locking schemes against machine learning attacks by decorrelating the circuit structure from the correct key, significantly reducing key prediction accuracy.
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