Polarity Engineering and 3D Integration of 2D Complementary Logic Circuits

Vertical three-dimensional integration of two-dimensional (2D) semiconductors enables scaling up logic layers, but the lack of controllable doping in 2D materials has impeded the development of complementary logic circuits. This work demonstrates a novel approach to engineer the carrier polarity in 2D semiconductors like MoS2 through van der Waals interfacial coupling, enabling the realization of vertically integrated complementary logic gates and circuits.